Difference between revisions of "Chapter 5"

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(Transconductance & Drain Resistance)
(Small-signal analysis)
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! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response
| Common-Source|| || || || ||
| Common-Source||<math>A_v>-1</math> || || || ||
| Common-Drain<br>Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low ||
| Common-Drain<br>Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low ||

Revision as of 15:15, 21 March 2010

Metal-oxide semiconductor field effect transistor (MOSFET)

Circuit symbols for various FETs
NMOS & PMOS in Cutoff
Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off)
IvsV mosfet.png
FET small-signal equivalent circuit

"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>

  • Enhancement: The electric field from the gate voltage forms an induced channel allowing current to flow.
  • Depletion: The channel is physically implanted rather than induced.
  • JFET: Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).

Threshold Voltage

  • The threshold voltage, V_{to}, is the minimum v_{GS} needed to move the transistor from the Cutoff to Triode region.
  • V_{to} is usually on the order of a couple of volts
V_{to} for various FETs
Type n-Channel p-Channel
Enhancement + -
Depletion - +
JFET - +
IMG 0292.JPG

Modes of operation

  • Cutoff
  • The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
  • Triode:
  • When v_{GS}=V_{to} is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
  • As v_{DS} increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
  • " Because of the tapering of the channel, its resistance becomes larger with increasing v_{DS}, resuling in a lower rate of increase of i_D." <ref>Electronics p. 291</ref>
  • Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?
  • Saturation:
  • When v_{DG}=V_{to} is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).

Device equations

Conditions for various modes of operation
Region v_{GS}\, v_{DS}\,
Cutoff v_{GS}<V_{to}\,
Triode  v_{GS} \ge V_{to} v_{DS} \le v_{GS}- V_{to}\,
Saturation  v_{GS} \ge V_{to} v_{DS} \ge v_{GS}- V_{to}\,
Boundry v_{GS}-v_{DS}=V_{to}\,
Alternate (Frohne) method
Region v_{GS}\, v_{DG}\,
Cutoff v_{GS}<V_{to}
Triode v_{GS}\ge V_{to} v_{DG} \le V_{to}
Saturation v_{GS}\ge V_{to} v_{DG} \ge V_{to}
Drain current
Region i_D
Cutoff 0
Triode K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]
Saturation K(v_{GS}-V_{to})^2\,
Boundry Kv^2_{DS}
Type K
JFET \frac{I_{DSS}}{V_{to}^2}
  • Device Parameters: KP=\mu_n C_{ox}
  • Surface Mobility: \mu_n, the electrons in the channel
  • Capacitance of the gate per unit area: C_{ox}

Transconductance & Drain Resistance

  • "Transconductance, g_m=2\sqrt{KI_{DQ}}, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of g_m." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
  • g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}
  • \frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}
  • Looking at the FET small-signal equivalent circuit, we can write i_d=g_m v_{gs}+\frac{v_{ds}}{r_d}, thus g_m=\frac{i_d}{v_{gs}} \bigg|_{v_{ds}=0}. Since these are small changes from the Q-point, we can write g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}. Similarly, we can write \frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}

Small-signal analysis

  1. Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
  2. Use the small-signal equivalent circuit to find the impedance and gains
Type Voltage Gain Current Gain Power Gain Input Impedance Output Impedance Frequency Response
Common-Source A_v>-1
Source Follower
A_v<1 A_i>1 G>1 High Low


Transistor Pros Cons
MOSFET *Draws no gate current
*Infinite input resistance
*Voltage-controlled current source
Gate protection needed to prevent static electricity from breaking down the insulation
BJT Current-controlled current source


  • How do you find rd?
  • Roughly what are the breakdown voltages for JFETs?
  • CMOS nand/nor gates
  • JFET only goes to IDSS?