Radio

2010-04-01T22:42:55Z

Fonggr:

Radio

2010-04-01T22:42:08Z

Fonggr:

*BPF:
:*What frequency range?
:*How to implement?

*Amplifier
:*Do we need an amplifier? Is the incoming signal large enough?

*LPF:
:*What frequency range?
:*How to implement?

*Oscillator:
:*Outputs a logic high and logic low. What is the best way to convert this to a co/sine wave (multiplex?)
:*What value are we looking for?

*Frequency Range:
:*FM is most likely too high to create
:*AM radio (car stereo) is about right. Find a station you want to tune to
:*96kHz of bandwidth (due to what the audio card can sample)

Radio

2010-04-01T22:15:03Z

Fonggr: New page: *BPF: :*What frequency range? :*How to implement? *Amplifier :*Do we need an amplifier? Is the incoming signal large enough? *LPF: :*What frequency range? :*How to implement? *Oscillato...

Electronics - Greg

2010-04-01T21:53:09Z

Fonggr:

*[[Electronics Questions]]
*[[Chapter 1]]
*[[Chapter 2]]
*[[Basic Op Amp circuits]]
*[[Superposition]]
*[[Chapter 2 problems]]
*[[Chapter 3]]
*[[Chapter 3 problems]]
*[[Chapter 4]]
*[[Chapter 4 problems]]
*[[Chapter 5]]
*[[Chapter 6]]
*[[Radio]]

Chapter 6

2010-03-25T06:00:17Z

Fonggr:

===Digital Logic Gates===
{| class="wikitable" border="1" style="text-align:center"
|+Boolean Algebra
!A!!B!!NAND <math>\overline{AB}</math>!!NOR <math>\overline{A+B}</math>!!XOR <math>A\oplus B</math>
|-
|0||0||1||1||0
|-
|0||1||1||0||1
|-
|1||0||1||0||1
|-
|1||1||0||0||0
|}

===De Morgan Laws & NAND Equivalent Gates===
*"If the variables in a logic expression are replaced by their inverses, and if the AND operation is replaced by OR, the OR operation is replaced by AND, and the expression is inverted, the resulting logic expression yields the same values as before the changes."<ref>Electronics p.353</ref>
*It is possible to create any combinatorial logic function with solely NAND (or NOR) gates
{| class="wikitable" border="1" style="text-align:center"
!Gate!!Symbol!!NAND equivalent
|-
|Inverter||<math>\overline{A}</math>||<math>\overline{AA}</math>
|-
|AND||<math>AB</math>||<math>\overline{(\overline{A}+\overline{B})}</math>
|-
|OR||<math>A+B</math>||<math>\overline{(\overline{A} \, \overline{B})}</math>
|}

===CMOS Inverter===
*Zero static power consumption
*<math>KP_p=\frac{1}{2}KP_n</math>, thus <math>\frac{W}{L}_p=2\frac{W}{L}_n</math> to maintain symmetric transfer characteristics.

===Questions===
*p.365: Why even have R_on?
*p.377: What problems are there with the NMOS pull-up?
*p.382: For CMOS, are the transistors in Triode or Saturation when they're in the "ON" state? How can we tell?

===References===
<references/>

Chapter 6

2010-03-24T22:15:47Z

Fonggr: /* Questions */

===Digital Logic Gates===
{| class="wikitable" border="1" style="text-align:center"
|+Boolean Algebra
!A!!B!!NAND <math>\overline{AB}</math>!!NOR <math>\overline{A+B}</math>!!XOR <math>A\oplus B</math>
|-
|0||0||1||1||0
|-
|0||1||1||0||1
|-
|1||0||1||0||1
|-
|1||1||0||0||0
|}

===De Morgan Laws & NAND Equivalent Gates===
*"If the variables in a logic expression are replaced by their inverses, and if the AND operation is replaced by OR, the OR operation is replaced by AND, and the expression is inverted, the resulting logic expression yields the same values as before the changes."<ref>Electronics p.353</ref>
*It is possible to create any combinatorial logic function with solely NAND (or NOR) gates
{| class="wikitable" border="1" style="text-align:center"
!Gate!!Symbol!!NAND equivalent
|-
|Inverter||<math>\overline{A}</math>||<math>\overline{AA}</math>
|-
|AND||<math>AB</math>||<math>\overline{(\overline{A}+\overline{B})}</math>
|-
|OR||<math>A+B</math>||<math>\overline{(\overline{A} \, \overline{B})}</math>
|}

===Questions===
*p.365: Why even have R_on?
*p.377: What problems are there with the NMOS pull-up?

===References===
<references/>

Chapter 6

2010-03-24T05:48:11Z

Fonggr:

===Digital Logic Gates===
{| class="wikitable" border="1" style="text-align:center"
|+Boolean Algebra
!A!!B!!NAND <math>\overline{AB}</math>!!NOR <math>\overline{A+B}</math>!!XOR <math>A\oplus B</math>
|-
|0||0||1||1||0
|-
|0||1||1||0||1
|-
|1||0||1||0||1
|-
|1||1||0||0||0
|}

===De Morgan Laws & NAND Equivalent Gates===
*"If the variables in a logic expression are replaced by their inverses, and if the AND operation is replaced by OR, the OR operation is replaced by AND, and the expression is inverted, the resulting logic expression yields the same values as before the changes."<ref>Electronics p.353</ref>
*It is possible to create any combinatorial logic function with solely NAND (or NOR) gates
{| class="wikitable" border="1" style="text-align:center"
!Gate!!Symbol!!NAND equivalent
|-
|Inverter||<math>\overline{A}</math>||<math>\overline{AA}</math>
|-
|AND||<math>AB</math>||<math>\overline{(\overline{A}+\overline{B})}</math>
|-
|OR||<math>A+B</math>||<math>\overline{(\overline{A} \, \overline{B})}</math>
|}

===Questions===
*p.365: Why even have R_on?
===References===
<references/>

Chapter 6

2010-03-24T03:33:09Z

Fonggr:

2010-03-24T02:44:09Z

Fonggr:

Chapter 5

2010-03-22T20:58:17Z

Fonggr: /* Small-signal analysis */

===Metal-oxide semiconductor field effect transistor (MOSFET) ===
[[Image:Mosfet.PNG|thumb|450px|Circuit symbols for various FETs]]
[[Image:MOS-Transistors-NMOS-and-PMOS.jpg|thumb|450px|NMOS & PMOS in Cutoff ]]
[[Image:NMOS-Transistors-Operation.png|thumb|450px| Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS]]
[[Image:IvsV_mosfet.png|thumb|450px| ]]
[[Image:IMG_0293.JPG|thumb|450px|FET small-signal equivalent circuit ]]
[[Image:Common-Gate_FET.png|thumb|450px|Common-Gate FET]]
"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).
===Threshold Voltage===
*The threshold voltage, <math>V_{to}</math>, is the minimum <math>v_{GS}</math> needed to move the transistor from the Cutoff to Triode region.
:*<math>V_{to}</math> is usually on the order of a couple of volts
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''<math>V_{to}</math> for various FETs'''
! Type !! n-Channel!! p-Channel
|-
| Enhancement|| + || -
|-
| Depletion|| - || +
|-
| JFET || - || +
|}
|STYLE="vertical-align: top" |
{|
[[Image:IMG_0292.JPG|x175px|none]]
|}
|}
===Modes of operation===
*'''Cutoff'''
:*The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
*'''Triode:'''
:*When <math>v_{GS}=V_{to}</math> is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
:*As <math>v_{DS}</math> increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
::*" Because of the tapering of the channel, its resistance becomes larger with increasing <math>v_{DS}</math>, resuling in a lower rate of increase of <math>i_D</math>." <ref>Electronics p. 291</ref>
::*'''Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?'''
*'''Saturation:'''
:*When <math>v_{DG}=V_{to}</math> is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).
===Device equations===
{|
|STYLE="vertical-align: top" |
{|class="wikitable" border="1" style="text-align:center"
|+ '''Conditions for various modes of operation'''
! Region!! <math>v_{GS}\,</math>!! <math>v_{DS}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}\,</math> ||
|-
| Triode|| <math> v_{GS} \ge V_{to}</math> || <math>v_{DS} \le v_{GS}- V_{to}\,</math>
|-
| Saturation || <math> v_{GS} \ge V_{to}</math>||<math>v_{DS} \ge v_{GS}- V_{to}\,</math>
|-
| Boundry || colspan="2" | <math>v_{GS}-v_{DS}=V_{to}\,</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Alternate (Frohne) method'''
! Region!! <math>v_{GS}\,</math> !! <math>v_{DG}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}</math> ||
|-
| Triode|| <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \le V_{to}</math>
|-
| Saturation || <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \ge V_{to}</math>
|}
|}
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Drain current'''
! Region!! <math>i_D</math>
|-
| Cutoff|| <math>0</math>
|-
| Triode|| <math>K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]</math>
|-
| Saturation || <math>K(v_{GS}-V_{to})^2\,</math>
|-
| Boundry || <math>Kv^2_{DS}</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''K'''
!Type !! K
|-
|Enhancement Depletion|| <math>\frac{1}{2}\mu_nC_{ox}\frac{W}{L}=\frac{1}{2}KP\frac{W}{L}</math>
|-
|JFET || <math>\frac{I_{DSS}}{V_{to}^2}</math>
|}
|}
*Device Parameters: <math>KP=\mu_n C_{ox}</math>
*Surface Mobility: <math>\mu_n</math>, the electrons in the channel
*Capacitance of the gate per unit area: <math>C_{ox}</math>
===Transconductance & Drain Resistance===
*"Transconductance, <math>g_m=2\sqrt{KI_{DQ}}</math>, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of <math>g_m</math>." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
*Looking at the FET small-signal equivalent circuit, we can write <math>i_d=g_m v_{gs}+\frac{v_{ds}}{r_d}</math>, thus <math>g_m=\frac{i_d}{v_{gs}} \bigg|_{v_{ds}=0}</math>. Since these are small changes from the Q-point, we can write <math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>. Similarly, we can write <math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>
*<math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>
*<math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>

===Small-signal analysis===
#Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
#Use the small-signal equivalent circuit to find the impedance and gains
{| class="wikitable" border="1" align="center"
|+
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response || Comments
|-align="center"
| Common-Source||<math>A_v>-1</math> || <math>A_i>-1</math> || <math>G > 1</math> || High || Low || ||Using <math>A_i=A_v*\frac{R_{in}}{R_L}</math>. '''Can you really have such a large voltage *and* current gain?'''
|-align="center"
| Common-Drain Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low || ||
|-align="center"
| Common-Gate || <math>\frac{g_mR_sr_dR_DR_L}{(R_DR_L+r_dR_L+r_dR_D)(R_i+R_S)}</math> || || || || || || http://users.ece.gatech.edu/mleach/ece3050/notes/mosfet/cgamp.pdf
|}

===MOSFET vs JFET vs BJT===
{| class="wikitable" border="1"
! Transistor!! Pros !! Cons
|-
| MOSFET|| rowspan="2" |*Draws no gate current *Infinite input resistance *Voltage-controlled current source || Gate protection needed to prevent static electricity from breaking down the insulation
|-
| JFET
|-
| BJT || Current-controlled current source||
|}
===Questions===
*How do you find rd?
*Roughly what are the breakdown voltages for JFETs?
*CMOS nand/nor gates
*JFET only goes to IDSS?
===References===
<references/>

Chapter 5

2010-03-22T03:45:09Z

Fonggr: /* Small-signal analysis */

===Metal-oxide semiconductor field effect transistor (MOSFET) ===
[[Image:Mosfet.PNG|thumb|450px|Circuit symbols for various FETs]]
[[Image:MOS-Transistors-NMOS-and-PMOS.jpg|thumb|450px|NMOS & PMOS in Cutoff ]]
[[Image:NMOS-Transistors-Operation.png|thumb|450px| Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS]]
[[Image:IvsV_mosfet.png|thumb|450px| ]]
[[Image:IMG_0293.JPG|thumb|450px|FET small-signal equivalent circuit ]]
[[Image:Common-Gate_FET.png|thumb|450px|Common-Gate FET]]
"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).
===Threshold Voltage===
*The threshold voltage, <math>V_{to}</math>, is the minimum <math>v_{GS}</math> needed to move the transistor from the Cutoff to Triode region.
:*<math>V_{to}</math> is usually on the order of a couple of volts
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''<math>V_{to}</math> for various FETs'''
! Type !! n-Channel!! p-Channel
|-
| Enhancement|| + || -
|-
| Depletion|| - || +
|-
| JFET || - || +
|}
|STYLE="vertical-align: top" |
{|
[[Image:IMG_0292.JPG|x175px|none]]
|}
|}
===Modes of operation===
*'''Cutoff'''
:*The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
*'''Triode:'''
:*When <math>v_{GS}=V_{to}</math> is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
:*As <math>v_{DS}</math> increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
::*" Because of the tapering of the channel, its resistance becomes larger with increasing <math>v_{DS}</math>, resuling in a lower rate of increase of <math>i_D</math>." <ref>Electronics p. 291</ref>
::*'''Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?'''
*'''Saturation:'''
:*When <math>v_{DG}=V_{to}</math> is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).
===Device equations===
{|
|STYLE="vertical-align: top" |
{|class="wikitable" border="1" style="text-align:center"
|+ '''Conditions for various modes of operation'''
! Region!! <math>v_{GS}\,</math>!! <math>v_{DS}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}\,</math> ||
|-
| Triode|| <math> v_{GS} \ge V_{to}</math> || <math>v_{DS} \le v_{GS}- V_{to}\,</math>
|-
| Saturation || <math> v_{GS} \ge V_{to}</math>||<math>v_{DS} \ge v_{GS}- V_{to}\,</math>
|-
| Boundry || colspan="2" | <math>v_{GS}-v_{DS}=V_{to}\,</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Alternate (Frohne) method'''
! Region!! <math>v_{GS}\,</math> !! <math>v_{DG}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}</math> ||
|-
| Triode|| <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \le V_{to}</math>
|-
| Saturation || <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \ge V_{to}</math>
|}
|}
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Drain current'''
! Region!! <math>i_D</math>
|-
| Cutoff|| <math>0</math>
|-
| Triode|| <math>K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]</math>
|-
| Saturation || <math>K(v_{GS}-V_{to})^2\,</math>
|-
| Boundry || <math>Kv^2_{DS}</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''K'''
!Type !! K
|-
|Enhancement Depletion|| <math>\frac{1}{2}\mu_nC_{ox}\frac{W}{L}=\frac{1}{2}KP\frac{W}{L}</math>
|-
|JFET || <math>\frac{I_{DSS}}{V_{to}^2}</math>
|}
|}
*Device Parameters: <math>KP=\mu_n C_{ox}</math>
*Surface Mobility: <math>\mu_n</math>, the electrons in the channel
*Capacitance of the gate per unit area: <math>C_{ox}</math>
===Transconductance & Drain Resistance===
*"Transconductance, <math>g_m=2\sqrt{KI_{DQ}}</math>, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of <math>g_m</math>." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
*Looking at the FET small-signal equivalent circuit, we can write <math>i_d=g_m v_{gs}+\frac{v_{ds}}{r_d}</math>, thus <math>g_m=\frac{i_d}{v_{gs}} \bigg|_{v_{ds}=0}</math>. Since these are small changes from the Q-point, we can write <math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>. Similarly, we can write <math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>
*<math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>
*<math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>

===Small-signal analysis===
#Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
#Use the small-signal equivalent circuit to find the impedance and gains
{| class="wikitable" border="1" align="center"
|+
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response || Comments
|-align="center"
| Common-Source||<math>A_v>-1</math> || <math>A_i>-1</math> || <math>G > 1</math> || High || Low || ||Using <math>A_i=A_v*\frac{R_{in}}{R_L}</math>. '''Can you really have such a large voltage *and* current gain?'''
|-align="center"
| Common-Drain Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low || ||
|-align="center"
| Common-Gate || || || || || ||
|}

===MOSFET vs JFET vs BJT===
{| class="wikitable" border="1"
! Transistor!! Pros !! Cons
|-
| MOSFET|| rowspan="2" |*Draws no gate current *Infinite input resistance *Voltage-controlled current source || Gate protection needed to prevent static electricity from breaking down the insulation
|-
| JFET
|-
| BJT || Current-controlled current source||
|}
===Questions===
*How do you find rd?
*Roughly what are the breakdown voltages for JFETs?
*CMOS nand/nor gates
*JFET only goes to IDSS?
===References===
<references/>

Chapter 5

2010-03-22T03:43:31Z

Fonggr: /* Small-signal analysis */

===Metal-oxide semiconductor field effect transistor (MOSFET) ===
[[Image:Mosfet.PNG|thumb|450px|Circuit symbols for various FETs]]
[[Image:MOS-Transistors-NMOS-and-PMOS.jpg|thumb|450px|NMOS & PMOS in Cutoff ]]
[[Image:NMOS-Transistors-Operation.png|thumb|450px| Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS]]
[[Image:IvsV_mosfet.png|thumb|450px| ]]
[[Image:IMG_0293.JPG|thumb|450px|FET small-signal equivalent circuit ]]
[[Image:Common-Gate_FET.png|thumb|450px|Common-Gate FET]]
"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).
===Threshold Voltage===
*The threshold voltage, <math>V_{to}</math>, is the minimum <math>v_{GS}</math> needed to move the transistor from the Cutoff to Triode region.
:*<math>V_{to}</math> is usually on the order of a couple of volts
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''<math>V_{to}</math> for various FETs'''
! Type !! n-Channel!! p-Channel
|-
| Enhancement|| + || -
|-
| Depletion|| - || +
|-
| JFET || - || +
|}
|STYLE="vertical-align: top" |
{|
[[Image:IMG_0292.JPG|x175px|none]]
|}
|}
===Modes of operation===
*'''Cutoff'''
:*The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
*'''Triode:'''
:*When <math>v_{GS}=V_{to}</math> is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
:*As <math>v_{DS}</math> increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
::*" Because of the tapering of the channel, its resistance becomes larger with increasing <math>v_{DS}</math>, resuling in a lower rate of increase of <math>i_D</math>." <ref>Electronics p. 291</ref>
::*'''Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?'''
*'''Saturation:'''
:*When <math>v_{DG}=V_{to}</math> is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).
===Device equations===
{|
|STYLE="vertical-align: top" |
{|class="wikitable" border="1" style="text-align:center"
|+ '''Conditions for various modes of operation'''
! Region!! <math>v_{GS}\,</math>!! <math>v_{DS}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}\,</math> ||
|-
| Triode|| <math> v_{GS} \ge V_{to}</math> || <math>v_{DS} \le v_{GS}- V_{to}\,</math>
|-
| Saturation || <math> v_{GS} \ge V_{to}</math>||<math>v_{DS} \ge v_{GS}- V_{to}\,</math>
|-
| Boundry || colspan="2" | <math>v_{GS}-v_{DS}=V_{to}\,</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Alternate (Frohne) method'''
! Region!! <math>v_{GS}\,</math> !! <math>v_{DG}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}</math> ||
|-
| Triode|| <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \le V_{to}</math>
|-
| Saturation || <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \ge V_{to}</math>
|}
|}
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Drain current'''
! Region!! <math>i_D</math>
|-
| Cutoff|| <math>0</math>
|-
| Triode|| <math>K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]</math>
|-
| Saturation || <math>K(v_{GS}-V_{to})^2\,</math>
|-
| Boundry || <math>Kv^2_{DS}</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''K'''
!Type !! K
|-
|Enhancement Depletion|| <math>\frac{1}{2}\mu_nC_{ox}\frac{W}{L}=\frac{1}{2}KP\frac{W}{L}</math>
|-
|JFET || <math>\frac{I_{DSS}}{V_{to}^2}</math>
|}
|}
*Device Parameters: <math>KP=\mu_n C_{ox}</math>
*Surface Mobility: <math>\mu_n</math>, the electrons in the channel
*Capacitance of the gate per unit area: <math>C_{ox}</math>
===Transconductance & Drain Resistance===
*"Transconductance, <math>g_m=2\sqrt{KI_{DQ}}</math>, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of <math>g_m</math>." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
*Looking at the FET small-signal equivalent circuit, we can write <math>i_d=g_m v_{gs}+\frac{v_{ds}}{r_d}</math>, thus <math>g_m=\frac{i_d}{v_{gs}} \bigg|_{v_{ds}=0}</math>. Since these are small changes from the Q-point, we can write <math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>. Similarly, we can write <math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>
*<math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>
*<math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>

===Small-signal analysis===
#Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
#Use the small-signal equivalent circuit to find the impedance and gains
{| class="wikitable" border="1" align="center"
|+
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response || Comments
|-align="center"
| Common-Source||<math>A_v>-1</math> || <math>A_i>-1</math> || <math>G > 1</math> || High || Low || ||Using <math>A_i=A_v*\frac{R_{in}}{R_L}</math>
|-align="center"
| Common-Drain Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low || ||
|-align="center"
| Common-Gate || || || || || ||
|}

===MOSFET vs JFET vs BJT===
{| class="wikitable" border="1"
! Transistor!! Pros !! Cons
|-
| MOSFET|| rowspan="2" |*Draws no gate current *Infinite input resistance *Voltage-controlled current source || Gate protection needed to prevent static electricity from breaking down the insulation
|-
| JFET
|-
| BJT || Current-controlled current source||
|}
===Questions===
*How do you find rd?
*Roughly what are the breakdown voltages for JFETs?
*CMOS nand/nor gates
*JFET only goes to IDSS?
===References===
<references/>

Chapter 5

2010-03-22T03:42:59Z

Fonggr:

===Metal-oxide semiconductor field effect transistor (MOSFET) ===
[[Image:Mosfet.PNG|thumb|450px|Circuit symbols for various FETs]]
[[Image:MOS-Transistors-NMOS-and-PMOS.jpg|thumb|450px|NMOS & PMOS in Cutoff ]]
[[Image:NMOS-Transistors-Operation.png|thumb|450px| Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS]]
[[Image:IvsV_mosfet.png|thumb|450px| ]]
[[Image:IMG_0293.JPG|thumb|450px|FET small-signal equivalent circuit ]]
[[Image:Common-Gate_FET.png|thumb|450px|Common-Gate FET]]
"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).
===Threshold Voltage===
*The threshold voltage, <math>V_{to}</math>, is the minimum <math>v_{GS}</math> needed to move the transistor from the Cutoff to Triode region.
:*<math>V_{to}</math> is usually on the order of a couple of volts
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''<math>V_{to}</math> for various FETs'''
! Type !! n-Channel!! p-Channel
|-
| Enhancement|| + || -
|-
| Depletion|| - || +
|-
| JFET || - || +
|}
|STYLE="vertical-align: top" |
{|
[[Image:IMG_0292.JPG|x175px|none]]
|}
|}
===Modes of operation===
*'''Cutoff'''
:*The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
*'''Triode:'''
:*When <math>v_{GS}=V_{to}</math> is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
:*As <math>v_{DS}</math> increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
::*" Because of the tapering of the channel, its resistance becomes larger with increasing <math>v_{DS}</math>, resuling in a lower rate of increase of <math>i_D</math>." <ref>Electronics p. 291</ref>
::*'''Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?'''
*'''Saturation:'''
:*When <math>v_{DG}=V_{to}</math> is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).
===Device equations===
{|
|STYLE="vertical-align: top" |
{|class="wikitable" border="1" style="text-align:center"
|+ '''Conditions for various modes of operation'''
! Region!! <math>v_{GS}\,</math>!! <math>v_{DS}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}\,</math> ||
|-
| Triode|| <math> v_{GS} \ge V_{to}</math> || <math>v_{DS} \le v_{GS}- V_{to}\,</math>
|-
| Saturation || <math> v_{GS} \ge V_{to}</math>||<math>v_{DS} \ge v_{GS}- V_{to}\,</math>
|-
| Boundry || colspan="2" | <math>v_{GS}-v_{DS}=V_{to}\,</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Alternate (Frohne) method'''
! Region!! <math>v_{GS}\,</math> !! <math>v_{DG}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}</math> ||
|-
| Triode|| <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \le V_{to}</math>
|-
| Saturation || <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \ge V_{to}</math>
|}
|}
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Drain current'''
! Region!! <math>i_D</math>
|-
| Cutoff|| <math>0</math>
|-
| Triode|| <math>K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]</math>
|-
| Saturation || <math>K(v_{GS}-V_{to})^2\,</math>
|-
| Boundry || <math>Kv^2_{DS}</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''K'''
!Type !! K
|-
|Enhancement Depletion|| <math>\frac{1}{2}\mu_nC_{ox}\frac{W}{L}=\frac{1}{2}KP\frac{W}{L}</math>
|-
|JFET || <math>\frac{I_{DSS}}{V_{to}^2}</math>
|}
|}
*Device Parameters: <math>KP=\mu_n C_{ox}</math>
*Surface Mobility: <math>\mu_n</math>, the electrons in the channel
*Capacitance of the gate per unit area: <math>C_{ox}</math>
===Transconductance & Drain Resistance===
*"Transconductance, <math>g_m=2\sqrt{KI_{DQ}}</math>, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of <math>g_m</math>." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
*Looking at the FET small-signal equivalent circuit, we can write <math>i_d=g_m v_{gs}+\frac{v_{ds}}{r_d}</math>, thus <math>g_m=\frac{i_d}{v_{gs}} \bigg|_{v_{ds}=0}</math>. Since these are small changes from the Q-point, we can write <math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>. Similarly, we can write <math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>
*<math>g_m=\frac{\partial i_D}{\partial v_{GS}}\bigg|_{Q-point}</math>
*<math>\frac{1}{r_d}=\frac{\partial i_D}{\partial v_{DS}}\bigg|_{Q-point}</math>

===Small-signal analysis===
#Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
#Use the small-signal equivalent circuit to find the impedance and gains
{| class="wikitable" border="1" align="center"
|+
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response || Comments
|-align="center"
| Common-Source||<math>A_v>-1</math> || <math>A_i>-1</math> || <math>G > 1</math> || High || Low || ||Using <math>A_i=A_v*\frac{R_{in}}{R_L}</math>
|-align="center"
| Common-Drain Source Follower|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low || ||
|-align="center"
| [[Common-Gate]] || || || || || ||
|}

===MOSFET vs JFET vs BJT===
{| class="wikitable" border="1"
! Transistor!! Pros !! Cons
|-
| MOSFET|| rowspan="2" |*Draws no gate current *Infinite input resistance *Voltage-controlled current source || Gate protection needed to prevent static electricity from breaking down the insulation
|-
| JFET
|-
| BJT || Current-controlled current source||
|}
===Questions===
*How do you find rd?
*Roughly what are the breakdown voltages for JFETs?
*CMOS nand/nor gates
*JFET only goes to IDSS?
===References===
<references/>

2010-03-21T21:43:36Z

Fonggr:

===Metal-oxide semiconductor field effect transistor (MOSFET) ===
[[Image:Mosfet.PNG|thumb|450px|Circuit symbols for various FETs]]
[[Image:MOS-Transistors-NMOS-and-PMOS.jpg|thumb|450px|NMOS & PMOS in Cutoff ]]
[[Image:NMOS-Transistors-Operation.png|thumb|450px| Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS]]
[[Image:IvsV_mosfet.png|thumb|450px| ]]
[[Image:IMG_0293.JPG|thumb|450px|FET small-signal equivalent circuit ]]

"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).

===Threshold Voltage===
*The threshold voltage, <math>V_{to}</math>, is the minimum <math>v_{GS}</math> needed to move the transistor from the Cutoff to Triode region.
:*<math>V_{to}</math> is usually on the order of a couple of volts
{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''<math>V_{to}</math> for various FETs'''
! Type !! n-Channel!! p-Channel
|-
| Enhancement|| + || -
|-
| Depletion|| - || +
|-
| JFET || - || +
|}
|STYLE="vertical-align: top" |
{|
[[Image:IMG_0292.JPG|x175px|none]]
|}
|}

===Modes of operation===
*'''Cutoff'''
:*The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
*'''Triode:'''
:*When <math>v_{GS}=V_{to}</math> is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
:*As <math>v_{DS}</math> increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.
::*" Because of the tapering of the channel, its resistance becomes larger with increasing <math>v_{DS}</math>, resuling in a lower rate of increase of <math>i_D</math>." <ref>Electronics p. 291</ref>
::*'''Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?'''
*'''Saturation:'''
:*When <math>v_{DG}=V_{to}</math> is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).

===Device equations===
{|
|STYLE="vertical-align: top" |
{|class="wikitable" border="1" style="text-align:center"
|+ '''Conditions for various modes of operation'''
! Region!! <math>v_{GS}\,</math>!! <math>v_{DS}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}\,</math> ||
|-
| Triode|| <math> v_{GS} \ge V_{to}</math> || <math>v_{DS} \le v_{GS}- V_{to}\,</math>
|-
| Saturation || <math> v_{GS} \ge V_{to}</math>||<math>v_{DS} \ge v_{GS}- V_{to}\,</math>
|-
| Boundry || colspan="2" | <math>v_{GS}-v_{DS}=V_{to}\,</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Alternate (Frohne) method'''
! Region!! <math>v_{GS}\,</math> !! <math>v_{DG}\,</math>
|-
| Cutoff|| <math>v_{GS}<V_{to}</math> ||
|-
| Triode|| <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \le V_{to}</math>
|-
| Saturation || <math>v_{GS}\ge V_{to} </math> || <math>v_{DG} \ge V_{to}</math>
|}
|}

{|
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+ '''Drain current'''
! Region!! <math>i_D</math>
|-
| Cutoff|| <math>0</math>
|-
| Triode|| <math>K [2(v_{GS}-V_{to})v_{DS}-v^2_{DS}]</math>
|-
| Saturation || <math>K(v_{GS}-V_{to})^2\,</math>
|-
| Boundry || <math>Kv^2_{DS}</math>
|}
|STYLE="vertical-align: top" |
{| class="wikitable" border="1" style="text-align:center"
|+'''K'''
!Type !! K
|-
|Enhancement Depletion|| <math>\frac{1}{2}\mu_nC_{ox}\frac{W}{L}=\frac{1}{2}KP\frac{W}{L}</math>
|-
|JFET || <math>\frac{I_{DSS}}{V_{to}^2}</math>
|}
|}

*Device Parameters: <math>KP=\mu_n C_{ox}</math>
*Surface Mobility: <math>\mu_n</math>, the electrons in the channel
*Capacitance of the gate per unit area: <math>C_{ox}</math>

===Transconductance & Drain Resistance===
*"Transconductance, <math>g_m=2\sqrt{KI_{DQ}}</math>, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of <math>g_m</math>." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>

===Small-signal analysis===
#Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
#Use the small-signal equivalent circuit to find the impedance and gains

{| class="wikitable" border="1" align="center"
|+
! Type!! Voltage Gain || Current Gain || Power Gain ||Input Impedance || Output Impedance|| Frequency Response
|-align="center"
| Common-Source|| <math>A_v<1</math>|| <math>A_i>1</math>|| <math>G>1</math> ||High || Low ||
|-align="center"
| Common-Drain Source Follower|| || || ||
|-align="center"
| Common-Gate || || || ||
|}

===MOSFET vs JFET vs BJT===
{| class="wikitable" border="1"
! Transistor!! Pros !! Cons
|-
| MOSFET|| rowspan="2" |*Draws no gate current *Infinite input resistance *Voltage-controlled current source || Gate protection needed to prevent static electricity from breaking down the insulation
|-
| JFET
|-
| BJT || Current-controlled current source||
|}

===Questions===
*How do you find rd?
*Roughly what are the breakdown voltages for JFETs?
*CMOS nand/nor gates
*JFET only goes to IDSS?

===References===
<references/>