Chapter 5

Metal-oxide semiconductor field effect transistor (MOSFET)

Circuit symbols for various FETs

NMOS & PMOS in Cutoff

Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off)
NMOS

FET small-signal equivalent circuit

Common-Gate FET

"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>

• Enhancement: The electric field from the gate voltage forms an induced channel allowing current to flow.
• Depletion: The channel is physically implanted rather than induced.
• JFET: Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).

Threshold Voltage

• The threshold voltage, $V_{to}$, is the minimum $v_{GS}$ needed to move the transistor from the Cutoff to Triode region.

• $V_{to}$ is usually on the order of a couple of volts

$V_{to}$ for various FETs Type n-Channel p-Channel Enhancement + - Depletion - + JFET - +

Modes of operation

• Cutoff

• The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.

• Triode:

• When $v_{GS}=V_{to}$ is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
• As $v_{DS}$ increases, the voltage between the gate and channel becomes smaller as you progress towards the drain. This results in the channel tapering off as you get closer to the drain.

• " Because of the tapering of the channel, its resistance becomes larger with increasing $v_{DS}$, resuling in a lower rate of increase of $i_{D}$." <ref>Electronics p. 291</ref>
• Why doesn't it just cut the current off completely when v_DS gets high enough? If it is pinched off, how does the current flow still?

• Saturation:

• When $v_{DG}=V_{to}$ is reached, the channel thickness at the drain end becomes zero (Enhancement, Depletion & JFET).

Device equations

Conditions for various modes of operation Region $v_{GS}\,$ $v_{DS}\,$ Cutoff $v_{GS}<V_{to}\,$ Triode $v_{GS}\geq V_{to}$ $v_{DS}\leq v_{GS}-V_{to}\,$ Saturation $v_{GS}\geq V_{to}$ $v_{DS}\geq v_{GS}-V_{to}\,$ Boundry $v_{GS}-v_{DS}=V_{to}\,$

Alternate (Frohne) method Region $v_{GS}\,$ $v_{DG}\,$ Cutoff $v_{GS}<V_{to}$ Triode $v_{GS}\geq V_{to}$ $v_{DG}\leq V_{to}$ Saturation $v_{GS}\geq V_{to}$ $v_{DG}\geq V_{to}$

Drain current Region $i_{D}$ Cutoff $0$ Triode $K[2(v_{GS}-V_{to})v_{DS}-v_{DS}^{2}]$ Saturation $K(v_{GS}-V_{to})^{2}\,$ Boundry $Kv_{DS}^{2}$

K Type K Enhancement Depletion ${\frac {1}{2}}\mu _{n}C_{ox}{\frac {W}{L}}={\frac {1}{2}}KP{\frac {W}{L}}$ JFET ${\frac {I_{DSS}}{V_{to}^{2}}}$

• Device Parameters: $KP=\mu _{n}C_{ox}$
• Surface Mobility: $\mu _{n}$, the electrons in the channel
• Capacitance of the gate per unit area: $C_{ox}$

Transconductance & Drain Resistance

• "Transconductance, $g_{m}=2{\sqrt {KI_{DQ}}}$, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of $g_{m}$." It is obtained at the cost of chip area.<ref>Electroincs p. 310</ref>
• Looking at the FET small-signal equivalent circuit, we can write $i_{d}=g_{m}v_{gs}+{\frac {v_{ds}}{r_{d}}}$, thus $g_{m}={\frac {i_{d}}{v_{gs}}}{\bigg |}_{v_{ds}=0}$. Since these are small changes from the Q-point, we can write $g_{m}={\frac {\partial i_{D}}{\partial v_{GS}}}{\bigg |}_{Q-point}$. Similarly, we can write ${\frac {1}{r_{d}}}={\frac {\partial i_{D}}{\partial v_{DS}}}{\bigg |}_{Q-point}$
• $g_{m}={\frac {\partial i_{D}}{\partial v_{GS}}}{\bigg |}_{Q-point}$
• ${\frac {1}{r_{d}}}={\frac {\partial i_{D}}{\partial v_{DS}}}{\bigg |}_{Q-point}$

Small-signal analysis

1. Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
2. Use the small-signal equivalent circuit to find the impedance and gains

Type	Voltage Gain	Current Gain	Power Gain	Input Impedance	Output Impedance	Frequency Response	Comments
Common-Source	$A_{v}>-1$	$A_{i}>-1$	$G>1$	High	Low		Using $A_{i}=A_{v}*{\frac {R_{in}}{R_{L}}}$. Can you really have such a large voltage *and* current gain?
Common-Drain Source Follower	$A_{v}<1$	$A_{i}>1$	$G>1$	High	Low
Common-Gate	${\frac {g_{m}R_{s}r_{d}R_{D}R_{L}}{(R_{D}R_{L}+r_{d}R_{L}+r_{d}R_{D})(R_{i}+R_{S})}}$						http://users.ece.gatech.edu/mleach/ece3050/notes/mosfet/cgamp.pdf

MOSFET vs JFET vs BJT

Transistor	Pros	Cons
MOSFET	*Draws no gate current *Infinite input resistance *Voltage-controlled current source	Gate protection needed to prevent static electricity from breaking down the insulation
JFET
BJT	Current-controlled current source

Questions

• How do you find r_d?
• Roughly what are the breakdown voltages for JFETs?
• CMOS nand/nor gates
• JFET only goes to I_DSS?

References

<references/>