# Difference between revisions of "Chapter 6"

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|OR||<math>A+B</math>||<math>\overline{(\overline{A} \, \overline{B})}</math> |
|OR||<math>A+B</math>||<math>\overline{(\overline{A} \, \overline{B})}</math> |
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+ | ===CMOS Inverter=== |
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+ | *Zero static power consumption |
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+ | *<math>KP_p=\frac{1}{2}KP_n</math>, thus <math>\frac{W}{L}_p=2\frac{W}{L}_n</math> to maintain symmetric transfer characteristics. |
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===Questions=== |
===Questions=== |
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*p.365: Why even have R_on? |
*p.365: Why even have R_on? |
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*p.377: What problems are there with the NMOS pull-up? |
*p.377: What problems are there with the NMOS pull-up? |
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+ | *p.382: For CMOS, are the transistors in Triode or Saturation when they're in the "ON" state? How can we tell? |
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===References=== |
===References=== |

## Latest revision as of 22:00, 24 March 2010

## Contents

### Digital Logic Gates

A | B | NAND |
NOR |
XOR |
---|---|---|---|---|

0 | 0 | 1 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 0 |

### De Morgan Laws & NAND Equivalent Gates

- "If the variables in a logic expression are replaced by their inverses, and if the AND operation is replaced by OR, the OR operation is replaced by AND, and the expression is inverted, the resulting logic expression yields the same values as before the changes."<ref>Electronics p.353</ref>
- It is possible to create any combinatorial logic function with solely NAND (or NOR) gates

Gate | Symbol | NAND equivalent |
---|---|---|

Inverter | ||

AND | ||

OR |

### CMOS Inverter

- Zero static power consumption
- , thus to maintain symmetric transfer characteristics.

### Questions

- p.365: Why even have R_on?
- p.377: What problems are there with the NMOS pull-up?
- p.382: For CMOS, are the transistors in Triode or Saturation when they're in the "ON" state? How can we tell?

### References

<references/>