Chapter 5

Metal-oxide semiconductor field effect transistor (MOSFET)

Circuit symbols for various FETs

"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>

• Enhancement: The electric field from the gate voltage forms an induced channel allowing current to flow.
• Depletion: The channel is physically implanted rather than induced. Thus, $V_{to}$ is the opposite polarity of the Enhancement mode.
• JFET: Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely). $V_{to}$ is the opposite polarity of the Enhancement mode.

Talk about the irregular pinched off shape of a JFET. Insert a photo.

Threshold Voltage

Type n-Channel p-Channel Enhancement + - Depletion - + JFET - +

Modes of operation NMOS & PMOS in Cutoff Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off) NMOS Cutoff The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows. Triode: The threshold voltage, $V_{to}$, is the minimum $v_{GS}$ needed to move the transistor from the Cutoff to Triode region. When this is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow. Note that $V_{to}$ can be positive or negative. $V_{to}$ is usually on the order of a couple of volts For small values of $v_{DS}$, $i_{D}$ is proportional to $v_{DS}$. The device behaves as a resistor whose value depends on $v_{GS}$. Is this true for Depletion and JFET? Saturation: "Now consider what happens if we continue to increase $v_{DS}$. Because of the current flow, the voltages between points along the channel and the source become greater as we move toward the drain. Thus, the voltage between gate and channel becomes smaller as we move toward the rain, resulting in a tapering of the channel thickness as illustrated in Figure 5.5. Because of the tapering of the channel, its resistance becomes larger with increasing $v_{DS}$, resuling in a lower rate of increase of $i_{D}$." <ref>Electronics p. 291</ref> $i_{D}$, $V_{to}$ and PMOS/NMOS Device equations Conditions for various modes of operation Region $v_{GS}\,$ $v_{DS}\,$ Cutoff $v_{GS}<V_{to}\,$ Triode $v_{GS}\geq V_{to}$ $v_{DS}\leq v_{GS}-V_{to}\,$ Saturation $v_{GS}\geq V_{to}$ $v_{DS}\geq v_{GS}-V_{to}\,$ Boundry $v_{GS}-v_{DS}=V_{to}\,$ Alternate (Frohne) method Region $v_{GS}\,$ $v_{DG}\,$ Cutoff $v_{GS}<V_{to}$ Triode $v_{GS}\geq V_{to}$ $v_{DG}\leq V_{to}$ Saturation $v_{GS}\geq V_{to}$ $v_{DG}\geq V_{to}$ Drain current Region $i_{D}$ $K$ (Enhancement/Depletion) $K$ (JFET) Cutoff $0$ ${\frac {W}{L}}{\frac {\mu _{n}C_{ox}}{2}}={\frac {W}{L}}{\frac {KP}{2}}$ ${\frac {I_{DSS}}{V_{to}^{2}}}$ Triode $K[2(v_{GS}-V_{to})v_{DS}-v_{DS}^{2}]$ Saturation $K(v_{GS}-V_{to})^{2}\,$ Boundry $Kv_{DS}^{2}$ Device Parameters: $KP=\mu _{n}C_{ox}$ Surface Mobility: $\mu _{n}$, the electrons in the channel Capacitance of the gate per unit area: $C_{ox}$ Pros and Cons Transistor Pros Cons MOSFET Draws no gate current Infinite input resistance Gate protection needed to prevent static electricity from breaking down the insulation JFET BJT Analysis Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves) Use the small-signal equivalent circuit to find the impedance and gains Small-signal equivalent circuits Insert photo "Transconductance, gm, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of gm."<ref>Electroincs p. 310</ref> Transconductance is defined as $g_{m}=2K(V_{GSQ}-V_{to})={\sqrt {2KP}}{\sqrt {W/L}}{\sqrt {I_{DQ}}}$. $i_{d}=g_{m}v_{gs}+{\frac {v_{ds}}{r_{d}}}$, where rd is the drain resistance Type Voltage Gain Current Gain Power Gain Input Impedance Output Impedance Frequency Response Common-Source $A_{v}<1$ $A_{i}>1$ $G>1$ High Low Source Follower Common-Gate Questions How do you find rd? Roughly what are the breakdown voltages for JFETs? CMOS nand/nor gates JFET only goes to IDSS? References <references/>