Chapter 5

Metal-oxide semiconductor field effect transistor (MOSFET)

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Circuit symbols for various FETs

"In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET (also commonly nMOS, pMOS)."<ref>http://en.wikipedia.org/wiki/MOSFET MOSFET - Wikipedia</ref>

• Enhancement: The electric field from the gate voltage forms an induced channel allowing current to flow.
• Depletion: The channel is physically implanted rather than induced. Thus, $V_{to}$ is the opposite polarity of the Enhancement mode.
• JFET: Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely). $V_{to}$ is the opposite polarity of the Enhancement mode.

Modes of operation

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NMOS & PMOS in Cutoff

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Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off)
NMOS

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• Cutoff
• Triode:

• The threshold voltage, $V_{to}$, is the minimum $V_{GS}$ needed to move the transistor from the Cutoff to Triode region. When is reached, a channel forms beneath the gate, allowing current to flow.

• $V_{to}$ is usually on the order of a couple of volts

• For small values of $V_{DS}$, $i_D$ is proportional to $V_{DS}$. The device behaves as a resistor whose value depends on $v_{GS}$

• Saturation:

• "Now consider what happens if we continue to increase $V_{DS}$. Because of the current flow, the voltages between points along the channel and the source become greater as we move toward the drain. Thus, the voltage between gate and channel becomes smaller as we move toward the rain, resulting in a tapering of the channel thickness as illustrated in Figure 5.5. Because of the tapering of the channel, its resistance becomes larger with increasing $v_{DS}$, resuling in a lower rate of increase of $i_D$." <ref>Electronics p. 291</ref>

Device equations

Conditions for various modes of operation Region $v_{GS}$ $v_{DS}$ Cutoff $v_{GS}<V_{to}$ Triode $v_{GS}\ge V_{to}$ $v_{DS}\le v_{GS}-V_{to}$ Saturation $v_{GS}\ge V_{to}$ $v_{DS}\ge v_{GS}-V_{to}$ Boundry $v_{GS}-v_{DS}=V_{to}$

Alternate (Frohne) method Region $v_{GS}$ $v_{DG}$ Cutoff $v_{GS}<V_{to}$ Triode $v_{GS}\ge V_{to}$ $v_{DG}\le V_{to}$ Saturation $v_{GS}\ge V_{to}$ $v_{DG}\ge V_{to}$

Drain current

Region	$i_D$	$K$ (Enhancement/Depletion)	$K$ (JFET)
Cutoff	$0$	$\frac{W}{L}\frac{{\mu }_n{C}_{ox}}{2}=\frac{W}{L}\frac{KP}{2}$	$\frac{I_{DSS}}{V_{to}^2}$
Triode	$K[2(v_{GS}-V_{to})v_{DS}-v_{DS}^2]$
Saturation	$K(v_{GS}-V_{to}{)}^2$
Boundry	$K{v}_{DS}^2$

• Device Parameters: $KP={\mu }_n{C}_{ox}$
• Surface Mobility: ${\mu }_n$, the electrons in the channel
• Capacitance of the gate per unit area: $C_{ox}$

Pros and Cons

Transistor	Pros	Cons
MOSFET	Draws no gate current Infinite input resistance	Gate protection needed to prevent static electricity from breaking down the insulation
JFET
BJT

Analysis

1. Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
2. Use the small-signal equivalent circuit to find the impedance and gains

Small-signal equivalent circuits

• "Transconductance, g_m, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of g_m."<ref>Electroincs p. 310</ref>
• Transconductance is defined as $g_m=2K(V_{GSQ}-V_{to})=\sqrt{2KP}\sqrt{W/L}\sqrt{I_{DQ}}$.

• $i_d=g_m{v}_{gs}+\frac{v_{ds}}{r_d}$, where r_d is the drain resistance

Type	Voltage Gain	Current Gain	Power Gain	Input Impedance	Output Impedance	Frequency Response
Common-Source	$A_v<1$	$A_i>1$	$G>1$	High	Low
Source Follower
Common-Gate

Questions

• What's the difference between the enhancement and depletion modes?
• NMOS and BJTs seem very similar. Why would you use one over the other?
• How do you find r_d?
• Roughly what are the breakdown voltages for JFETs?
• Learn how to check for operating regions via V_gs & V_ds as compared to V_to.
• CMOS nand/nor gates
• JFET only goes to I_DSS
• Small signal model of mosfets

References

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