Chapter 5: Difference between revisions

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"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Enhancement''': The electric field from the gate voltage forms an induced channel allowing current to flow.
*'''Depletion''': The channel is physically implanted rather than induced. Thus, <math>V_{to}</math> is the opposite polarity of the Enhancement mode.
*'''Depletion''': The channel is physically implanted rather than induced.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely). <math>V_{to}</math> is the opposite polarity of the Enhancement mode.
*'''JFET''': Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).
'''''Talk about the irregular pinched off shape of a JFET. Insert a photo.'''''
'''''Talk about the irregular pinched off shape of a JFET. Insert a photo.'''''


===Threshold Voltage===
===Threshold Voltage===

Revision as of 13:28, 21 March 2010

Metal-oxide semiconductor field effect transistor (MOSFET)

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Circuit symbols for various FETs
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NMOS & PMOS in Cutoff
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Triode (Linear) and Saturation (B.P.O = Beyond Pinch Off)
NMOS
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"The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain."<ref>Wikipedia: Field-effect transistor http://en.wikipedia.org/wiki/Field-effect_transistor</ref>

  • Enhancement: The electric field from the gate voltage forms an induced channel allowing current to flow.
  • Depletion: The channel is physically implanted rather than induced.
  • JFET: Charge flows through a semiconducting channel (between the source and drain). Applying a bias voltage to the gate terminal impedes the current flow (or pinches it off completely).

Talk about the irregular pinched off shape of a JFET. Insert a photo.

Threshold Voltage

  • The threshold voltage, Vto, is the minimum vGS needed to move the transistor from the Cutoff to Triode region.
  • Vto is usually on the order of a couple of volts
Vto for various FETs
Type n-Channel p-Channel
Enhancement + -
Depletion - +
JFET - +
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Modes of operation

  • Cutoff
  • The channel has not been created (Enhancement) or is pinched off (Depletion & JFET). No current flows.
  • Triode:
  • When Vto is reached, a channel forms beneath the gate (Enhancement) or is no longer pinched off (Depletion & JFET), allowing current to flow.
  • For small values of vDS, iD is proportional to vDS. The device behaves as a resistor whose value depends on vGS. Is this true for Depletion and JFET?
  • Saturation:
  • "Now consider what happens if we continue to increase vDS. Because of the current flow, the voltages between points along the channel and the source become greater as we move toward the drain. Thus, the voltage between gate and channel becomes smaller as we move toward the rain, resulting in a tapering of the channel thickness as illustrated in Figure 5.5. Because of the tapering of the channel, its resistance becomes larger with increasing vDS, resuling in a lower rate of increase of iD." <ref>Electronics p. 291</ref>

Device equations

Conditions for various modes of operation
Region vGS vDS
Cutoff vGS<Vto
Triode vGSVto vDSvGSVto
Saturation vGSVto vDSvGSVto
Boundry vGSvDS=Vto
Alternate (Frohne) method
Region vGS vDG
Cutoff vGS<Vto
Triode vGSVto vDGVto
Saturation vGSVto vDGVto
Drain current
Region iD K
(Enhancement/Depletion)
K
(JFET)
Cutoff 0 WLμnCox2=WLKP2 IDSSVto2
Triode K[2(vGSVto)vDSvDS2]
Saturation K(vGSVto)2
Boundry KvDS2
  • Device Parameters: KP=μnCox
  • Surface Mobility: μn, the electrons in the channel
  • Capacitance of the gate per unit area: Cox

Pros and Cons

Transistor Pros Cons
MOSFET Draws no gate current
Infinite input resistance
Gate protection needed to prevent static electricity from breaking down the insulation
JFET
BJT

Analysis

  1. Analyze the DC circuit to find the Q-point (using nonlinear device equations or characteristic curves)
  2. Use the small-signal equivalent circuit to find the impedance and gains

Small-signal equivalent circuits

Insert photo

  • "Transconductance, gm, is an important parameter in the design of amplifier circuits. In general, better performance is obtained with higher values of gm."<ref>Electroincs p. 310</ref>
  • Transconductance is defined as gm=2K(VGSQVto)=2KPW/LIDQ.
  • id=gmvgs+vdsrd, where rd is the drain resistance


Type Voltage Gain Current Gain Power Gain Input Impedance Output Impedance Frequency Response
Common-Source Av<1 Ai>1 G>1 High Low
Source Follower
Common-Gate

Questions

  • How do you find rd?
  • Roughly what are the breakdown voltages for JFETs?
  • CMOS nand/nor gates
  • JFET only goes to IDSS?

References

<references/>